CONTEXT

The conventional 1-Transistor+1-Capacitor DRAM is extensively used in the semiconductor industry for manufacturing high density dynamic memories. Beyond the 45nm node, the DRAM industry will need new concepts avoiding the miniaturization issue of the memory-cell capacitor. The most attractive solution is to suppress the storage capacitor and use the floating body of SOI transistors to store the charge. Several 1T-DRAM devices have been already proposed, but they are difficult to scale due to the thick body needed for the coexistence of electrons and holes. The patent proposed here introduces a totally novel 1T-DRAM memory device based on the coupling of majority and minority carriers in highly-scaled Fully Depleted Silicon On Insulator transistors (FD-SOI)