The performance requirements of image processing applications have continuously increased the computing power of implementation platforms, especially when they are executed under real time constraints. The image processing applications may consist of different image standards, or different algorithms used at different stages of the processing chain.

The computing paradigm using reconfigurable architectures promises an intermediate trade-off between flexibility and performance.

Reconfigurable architectures can exploit fine-grain (more suitable for low level and medium level operations in the image processing chain) and coarse-grain parallelism (more suitable for high level operations in the image processing chain). Many reconfigurable architectures have been constructed specifically for image processing using different processors and dedicated circuits such as ASICs and FP