In the last few years, it has been proposed a new method for reconfiguring partially a FPGA. This method is well known as partial and dynamic FPGA reconfiguration from Virtex (Xilinx).

The goal is to configure partially the FPGA for each kind of function that must be run. Therefore the silicon size of the FPGA is considerably decreased, as there is no need to implement all functions that could one day be used.

However, this method implies to memorize the reconfiguration data for all applications that can be run on the FPGA.

Then, the silicon area won in the FPGA is wasted by memories.